Initial Ideas

The diagram bellow represents an initial idea for a FPGA computational device analogous to a hypercolumn (HC). The FPGA itself would contain the initial algorithms related to pattern recognition and decision making, successful matches and winning decisions data would then be stored on the SRAM to be used by the next HC interaction (or firmware update). The included µcontroller manages the reprogramming via the ISP protocol using the native JTAG interface found in FPGA devices.

Both HC and µcontroller have dedicated communication buses, where the HC addresses other HCs and works in parallel; µcontrollers would receive firmware updates to be programmed via a bus addressable by the HCs. It is important to note that data belonging to each set does not travel via the same channel, with the only exception being when HCs submit a new firmware to one or many µcontrollers.

A block diagram for a FPGA based hypercolumn